1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which has N-type diffusion layers and P-type diffusion layers on a semiconductor substrate and has a compound film of a semiconductor and a metal on each of the surfaces of the N-type and P-type diffusion layers.
2. Description of the Related Art
To realize a high-speed fine semiconductor device, the sheet resistance of a diffusion layer must be reduced. As one means for this purpose, a compound film of a semiconductor and a metal is formed on the surface of the diffusion layer.
FIGS. 1A to 1D show a conventional method of manufacturing a CMOS (Complementary Metal Oxide Semiconductor) transistor having such a compound film on the surface of a source/drain region. According to the conventional method, as shown in FIG. 1A, an SiO.sub.2 film 12 is selectively formed on the surface of an Si substrate 11 to define isolation regions. SiO.sub.2 films 15 are formed as gate oxide films on the surfaces of active regions for both an NMOS (N channel MOS) region 13 and a PMOS (P channel MOS) region 14.
Then, gate electrodes are formed by polycrystalline Si films 16, and an N.sup.- -type diffusion layer 17 and a P.sup.- -type diffusion layer 18 are formed as LDD (Lightly Doped Drain) regions in the NMOS region 13 and the PMOS region 14, respectively. A sidewall spacer consisting of an SiO.sub.2 film 21 is formed on the side surface of the polycrystalline Si film 16, and an SiO.sub.2 film 22 is deposited to a film thickness of about 10 nm on the entire surface by an atmospheric pressure CVD (Chemical Vapor Deposition) method, as shown in FIG. 1B.
As shown in FIG. 1C, only the PMOS region 14 is covered with a resist 23. As.sup.+ ions 24 are implanted into only the NMOS region 13 via the SiO.sub.2 film 22 at an acceleration energy of 30 keV and a dose of 3.times.10.sup.15 cm.sup.-2, forming N.sup.+ -type diffusion layers 25 as the source and drain regions of the NMOS transistor.
After the resist 23 is removed, as shown in FIG. 1D, only the NMOS region 13 is covered with a resist 26. BF.sub.2.sup.+ ions 27 are implanted into only the PMOS region 14 via the SiO.sub.2 film 22 at an acceleration energy of 30 keV and a dose of 3.times.10.sup.15 cm.sup.-2, forming P.sup.+ -type diffusion layers 28 as the source and drain regions of the PMOS transistor.
Thereafter, although not shown, the resist 26 and the SiO.sub.2 film 22 are removed. A refractory metal film deposited on the entire surface, the Si substrate 11, and the polycrystalline Si film 16 are silicified to self-aligningly form a refractory metal silicide film on only each of the surfaces of the diffusion layers 25 and 28 and the polycrystalline Si film 16. Source and drain electrodes, a passivation film, and the like are formed to complete the CMOS transistor.
However, As is smaller in diffusion coefficient than B or the like. If the As.sup.+ ions 24 are implanted via the SiO.sub.2 film 22, as in the related art described above, only the diffusion layers 25 having shallow junctions can be formed. For this reason, alloy spikes tend to be formed in forming the refractory metal silicide film on the surface of the diffusion layer 25, and junction leakage easily occurs in each diffusion layer 25. It is difficult to manufacture a highly reliable CMOS transistor.
Since only the diffusion layers 25 having shallow junctions can be formed, as described above, it is difficult to decrease the impurity concentration on the surface of the diffusion layer 25. Further, since the As.sup.+ ions 24 are implanted via the SiO.sub.2 film 22, oxygen is mixed in the Si substrate 11 due to the knock-on effect. As a result, a silicification reaction for forming the refractory metal silicide film on the surface of the diffusion layer 25 is suppressed. It is also difficult to manufacture a CMOS transistor having the diffusion layers 25 whose sheet resistance is as sufficiently low as several .OMEGA./.quadrature..
If no SiO.sub.2 film 22 is deposited on the Si substrate 11 in order to form the diffusion layers 25 having deep junctions and suppress the knock-on effect, F of the BF.sub.2.sup.+ 27 is mixed in the Si substrate 11 to suppress a silicification reaction for forming the refractory metal suicide film on the surface of each diffusion layer 28. It becomes difficult to manufacture a CMOS transistor having the diffusion layers 28 whose sheet resistance is sufficiently low.
In addition, if no SiO.sub.2 film 22 is deposited on the Si substrate 11, it becomes difficult to form the diffusion layers 28 having shallow junctions because the diffusion coefficient of B is large. The short channel effect of the PMOS transistor is conspicuous, and it also becomes difficult to manufacture a highly reliable CMOS transistor.